Image Smoothing Based On FPGA

Programmable logic is emerging as an attractive solution for many digital image processing applications. As image sizes and bit depths grow


Abstract
Programmable logic is emerging as an attractive solution for many digital image processing applications. As image sizes and bit depths grow larger, software has become less useful in the image processing, Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of algorithms suited to image processing applications, the unique architecture of the FPGA has allowed the technology to be used in many such applications encompassing all aspects of image processing.
Image smoothing is one of image processing applications, it often done to reduce the effect of pixel noise in images. This paper presents VHDL architectures (that allow description of the structure design of FPGA) to implement two of image smoothing filters: a) averaging filters b) median filters This research is also applying the filters on FPGA. The results proves high-speed performance of the algorithms that rely on hardware and software compared to software alone, as it appeared very big difference in the speed of execution, depending on the hardware devices that showed the speed of the implementation of the scale of nanosecond, while the software application of algorithms is measured in seconds.
The software was implemented in this research using MATLAB 2010 language code as well as the VHDL language to deal with use of FPGA device, which was of a kind (Xilinx XC3S500E Spartan-3E).

Introduction
Image processing is considered to be one of the most rapidly evolving areas of information technology, with growing applications in all fields of knowledge. It constitutes a core area of research within the computer science and engineering disciplines given the interest of potential applications ranging from image enhancing, to automatic image understanding, robotics and computer vision. The performance requirements of image processing applications have continuously increased the demands on computing power, especially when there are real time constraints. Image processing applications may consist of several low level algorithms applied in a processing chain to a stream of input images. In order to accelerate image processing, there are different alternatives ranging from parallel computers to specialized Application Specific Integrated Circuits (ASIC) architectures. The computing paradigm using reconfigurable architectures based on Field Programmable Gate Arrays (FPGAs) promises an intermediate trade-off between flexibility and performance [1].
Various techniques have been developed in Image Processing during the last four to five decades. Most of the techniques are developed for enhancing images obtained from unmanned spacecrafts, space probes and military reconnaissance flights. Image Processing systems are becoming popular due to easy availability of powerful personnel computers, large size memory devices, graphics software etc. [2].
Filtering is fundamental operation in image processing, it can be used for image enhancement, noise reduction, edge detection, and sharpening, the concept of filtering has been applied in the frequency domain, where it rejects some frequency components while accepting others. In the spatial domain, filtering is a pixel neighborhood operation. Commonly used spatial filtering techniques include: (median filtering, average filtering, Gaussian filtering, etc.) [3]. The filtering function sometimes is called filter mask, or filter kernel. They can be broadly classified into two different categories: linear filtering and order-statistic filters. The common elements of a filter are the neighborhood including the pixel itself. Typically the neighborhood is a rectangular of different size, for example 3×3, 5×5… and smaller than the image itself [4] [5].
Neighborhood of pixels is also called windowing operators that are use a window to calculate their output. For example, windowing operator may perform an operation like finding the average of all pixels in the neighborhood of a pixel. The pixel around which the window is found is called the origin. Figure 1, shows a 3×3 pixel window and the corresponding origin. The work in this paper is based on the usage of gray scale image smoothing using these pixel windows to calculate their output. Although a pixel window may be of any size and shape, a square 3x3 size was chosen for this application because it is large enough to work properly and small enough to implement efficiently on hardware.

Related work
Image smoothing algorithms are particularly suitable for implementation on FPGA, due to the parallelisms that may be exploited. Due to use of microcontroller or microprocessor instruction level parallelism is achieved. Research has been conducted to improve speed by designing system block by block.
Suhaib A. Fahmy suggested An hardware implementation of a median filter and use FIFO buffer to sort the samples for the window over which the median must be found [7], Anthony Edward Nelson also use FIFO buffer to sort the samples for the window over which the median must be found [6].
In this work pointer is using to reach the positions in RAM instead of using the first in first out implementation (FIFO) which is reduce the complexity of the algorithms implementation, also it reduce the size of the algorithms.

Smoothing/Averaging Filters
To smooth an image might do a N×N pixel moving window average of image -e.g. with the 3×3 filter below. Place centre pixel of window over given pixel; multiply pixels of image with pixels in window, sum results and copy as value of output pixel. Then shift window one place to right or down and repeat; the operation is called convolution [8].
The average filtering is also called mean filtering, where the output pixel value is the mean of its neighborhood. Thus, the filtering mask is as show in equation (1) [4]: The design of the averaging filter algorithm in VHDL was difficult problem. This was because the averaging filter algorithm uses adders, and dividers to calculate its output. On FPGAs, use of mathematics tends to slow down performance.
Addition is instantiated using simple (+) signs in the VHDL code. The VHDL synthesis tool provides mapping to efficient hardware mathematics designs for it.
Hardware dividers on FPGAs are quite large and slow, we use the bit shifting method of division. Since this is only possible with powers of two, a divide by 8 was implemented instead of a divide by 9, as was planned in the algorithm's design; Figure 2 shows a sketch representation of the mathematics of the hardware averaging filter; wile figure 3 shows the schematic design for the average filtering (the implementation of array, registers, adder and divider); figure 4 shows the simulation time result of average filtering in VHDL, and figure 5 shows the image after applying the average filtering in MATLAB and in VHDL. Finally, figure  6 shows the histogram for image after average filtering in MATLAB, VHDL and the histogram difference between the two images.   Variable used as a signal in the design Variable used for inputs and outputs port in the design

Smoothing/Median Filters
A median filter is a non-linear digital filter which is able to preserve sharp signal changes and is very effective in removing impulse noise (or salt and pepper noise) [9].
An impulse noise has a gray level with higher or lower value that is different from the neighborhood point [10]. Linear filters have no ability to remove this type of noise without affecting the distinguishing characteristics of the signal. Median filters have remarkable advantages over linear filters for this particular type of noise [11]. Therefore median filter is very widely used in digital signal and image/video processing applications. A standard median operation is implemented by sliding window of odd size (e.g. 3×3 window) over an image. At each window position the sampled values of signal or image are sorted, and the median value of the samples replaces the sample in the center of the window as shown in Figure 7.

Figure7; Graphic Depiction of median Filter Operation [6]
The structure in Figure 8 represents hardware design for sorting algorithm in VHDL.
Every r xx box is a register and every c xx box is a compare unit, consisting of a simple decision.
This design is accomplished quite simply in VHDL by using the following if/else statement [6]:   Figure 9 shows the schematic design for the median filter (the implementation of array, registers, adder and divider).    Figure 10 shows the simulation time result of median filter in VHDL. Figure 10; the simulation result of median filter Figure 11 shows the image after applying the median filter in MATLAB and in VHDL, Figure 12 shows the histogram for image after median filter in MATLAB, VHDL and the histogram difference between the two images.  Figure 13 shows the image after applying the median filter for removing salt and pepper noise in MATLAB and in VHDL, Figure 14 shows the histogram for image after median filter in MATLAB, VHDL and the histogram difference between the two images.

Conclusion and Result Discussion:
This work presents the implementation of two filters for image smoothing, (average filtering and median filter), on FPGA Xilinx XC3S500E Spartan-3E, the two filters are implemented using VHDL by using windowing operators that are use a window to calculate the outputs. The resulted image gets from VHDL are compared with the results get from MATLAB and found the RMSE, PSNR, MSE, and Correlation between the images, and the results show that the two images are almost the same. As shown in table 1 and 2, the Peak signal-to-noise ratio (PSNR) is high it generally indicates that the reconstruction is of higher quality, the mean square error (MSE) is small between two images that's mean the best explaining the variability in the observations, and the correlation value is closest to one that's mean there are little different between the images.  Many point could be concluded from the proposed work that is: 1. The hardware implementation gives the application higher efficiency and lower time as shown in table (4).